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M64893AGP
SERIAL INPUT PLL FREQUENCY SYNTHES IZER FOR TV/VCR
REJ03F0008-0100Z Rev.1.00 Jul.25.2003
Description
The M64093FP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using BiCMOS process. It contains prescaler with operating up to. 1.0 GHz, 4 band driver and a tuning amplifier for direct tuning.
Features
* * * * * * * * * * 4 integrated PNP band switching drivers (lo = 40 mA, Vsat = 0.2 V typ@Vcc1 to 13.2 V) Built-in tuning amplifier for direct tuning (33 V) Low power dissipation (lcc = 24 mA, at Vcc = 5 V) Built-in prescaler with input amplifier (Fmax = 1.0 GHz) PLL lock/unlock status display output (built-in pull-up resistor) Reference driver (Division radio 1/640) Serial data input (3 wire Bus) Built-in power on reset 16pin -plastic mold mini flat package (16pin SSOP) Without protection diode at CLK,DATA,ENA
Application
* TV,VCR tuners
Block Diagram
Xin
16
ENA DATA
15 14
CLK
13
LD
12
Vcc3 Vtu
11 10
Vin
9
19-BIT SHIFT REGISTER OSC DIVIDER
10-BIT MAIN COUNTER Vc c 1
10 LOCK DETECTOR
1/32,1/33
5-BIT SWALLOW COUNTER
5 PHASE DETECTOR 4 CHARGE PUMP
1/8
P.O. RESET
BIAS
BAND DRIVER
1
2
3
4
5
6
7
8
fin
GND
Vcc1
Vcc2
BS4
BS3
BS2
BS1
Rev.1.00, Jul.25.2003, page 1 of 11
M64893AGP
Pin Description
Symbol fin GND Vcc1 Vcc2 BS4 BS3 BS2 BS1 Vin Pin No. 1 2 3 4 5 6 7 8 9 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V Power supply voltage terminal. 5.0 V+/-0.5 V Power supply voltage terminal. Vcc1 to 13.2 V PNP open collector method is used. When the band switching data is "H", the output is "ON". When it is "L", the output is "OFF". This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f1/N) is lead compared to the reference frequency (fref), the "source" current state becomes active. If it is lag, the same, the high impedance state be comes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35 V When 19 bit data is input, lock detector is output. When 27 bit data is input, lock detector is output. the programmable divider output and reference divider output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freg. divider set falls. This is normally at an "L". When this is at "H", data and clock signals are received. Data is read into the latch when the 19th pulse of the clock signal falls. 4.0MHz crystal oscillator connected.
Filter input (Charge pump output)
Vtu Vcc3 LD
10 11 12
Tuning output Power supply voltage 3 Lock detect output
CLOCK DATA ENABLE
13 14 15
Clock input Data input Enable input
X in
16
This is connected to the Crystal oscillator.
Pin Arrangement
PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 fin G ND Vcc1 Vcc BS4 BAND SWITCHING OUTPUTS BS BS BS1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
Xin EN A DATA CLK LD Vcc2 Vtu Vin
CRYSTAL OSCILLATOR ENABLE INPUT DATAINPUT LOCK INPUT LOCK OUTPUT SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT
9
OUTLINE 16P2Z
Rev.1.00, Jul.25.2003, page 2 of 11
M64893AGP
Method of Setting Data
The programmable divider uses 15bits Setting up the band switching output uses 4bits. The test mode data use s 8bits. The total bits used is 27bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in the 4th pulse of the clock signal. The programmable driver data is read into the fall of the 19th pulse of the clock signal .When the enable signal goes to "L" Before the 19th pulse of the enable signal, only the band switching data is updated and other data is ignored.
ENA DATA CLK
BAND SWITCHING DATA MAIN COUNTER DIVISION RATIO SETTING READ INTO LATCH SWALLOW COUNTER DIVISION RATIO SETTING READ INTO LATCH BS4 BS3 BS2 BS1 29 M9 28 M8 27 M7 26 M6 25 24 M5 M4 23 M3 22 M2 21 20 M1 M0 24 23 22 21 20 S4 S3 S2 S1 S0
How to Set The Dividing Radio of The Programmable Divider
Total division N is given by the following from formulas in addition to the prescaler used the previous stage.
N = 8*(32 M+S) M: 10 bit main counter division S: 5 bit swallow counter division
The M and S counters are binary the possible ranges of division are follows.
32 M 1023 0 S 31 Therefore, the rage of division N is 8,192 to 262, 136. The tuning frequency fvco is given in the following equations. fvco = fref*N = 6.25*8*(32M+S) = 50.0*8*(32M+S) [KHz]
Therefore, the tuning frequency range is from 51.2 MHz to 1000 MHz
Rev.1.00, Jul.25.2003, page 3 of 11
M64893AGP
Test Mode Data Set Up Method
The data for the test mode uses from 20 to 27 bits. Data is latched when the 27th clock signal falls.
(1) When transferring 3-wire 27 bit data ENA
1
19 20
MAIN COUNTER DIVISION RATIO SETTING
X CP T 2 T 1
27
T O RSa RSbOS
CLK
BAND SWITCHING DATA SWALLOW COUNTER DIVISION RATIO SETTING TEST DATA SETTING READ INTO LATCH
(2) Test Mode Bit Set Up X CP T0, T1,&T2 RSa, Rsa OS :Random, 0 or 1.normal "0" :Set up the charge pump current value :Set up test modes :Set the frequency division of the reference frequency :Set up the tuning amplifier
Setting Up the Charge Pump Current of The Phase Comparator
CP 0 1 Charge pump current 50 A 250 A Mode Normal Test
Setting Up The Test Mode
T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump Normal operation High impedance Sink Source High impedance High impedance 12 pin output LD LD LD LD fref f1/N Mode Test Test Test Test Test Test
Rev.1.00, Jul.25.2003, page 4 of 11
M64893AGP
Set Up for The Reference Frequency Division Radio
RSa 0 1 X RSb 1 1 0 Division radio 1/512 1/1024 1/640
Set Up The Tuning Amplifier
OS 0 1 Tuning voltage output ON OFF mode Normal Test
Power On Reset Operation (Initial State The Power is Turned ON)
* * * * * * BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency division radio Lock output :OFF :high impedance :OFF :250 :1/640 :H
Rev.1.00, Jul.25.2003, page 5 of 11
M64893AGP
Timing Diagram
tr ENABLE
90% 1.5V 90%
tf VIH
10%
10%
tINT
90% 90%
tINT
1.5V
VIL VIH VIL VIH VIL
tBT
DATA
10% tr 90% 1.5V 10% 90% tr 10% tf 10% tf
CLOCK tPWC tSU(D) tSU(E)
tH(D)
tH(E)
tBCL
Crystal Oscillator Connection Diagram
16
Crystal oscillator characteristics Actual resistance : less than300ohm
18pF 4MHz
Load capacitance : 20pF
Rev.1.00, Jul.25.2003, page 6 of 11
M64893AGP
Absolute Maximum Ratings
(Ta = -20C to 75C unless otherwise noted)
Parameter Standby voltage1 Standby voltage2 Standby voltage3 Input voltage Output voltage Voltage applied when the band output current is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Symbols Vcc1 Vcc2 Vcc3 VI VBSOFF IBSON tBSON Pd Topr Tstg Tstg Max.ratings 6.0 14.4 36.0 6.0 6.0 14.4 50.0 10 350 -20 to +75 -40 to +125 Units V V V V V V mA sec mW C C Conditions Pin3 Pin4 Pin11 Not to exceed Vcc1 Pin 12
Per 1 band output circuit 50 mA per 1 band output circuit 3 cicuits are pn at same time Ta = 75C
Recommended Operating Conditions
(Ta = -20C to 75Cunless otherwise noted)
Parameter Standby voltage1 Standby voltage2 Standby voltage3 Operating frequency(1) Operating frequency(2) Band output current 5 to 8 Symbols Vcc1 Vcc2 Vcc3 fopr2 fopr2 IBDL Ratings 4.5 to 5.5 5.0 to 3.2 30 to 35 4.0 80 to 100 0 to 40 Units V V V MHz MHz mA Conditions
Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time.
Rev.1.00, Jul.25.2003, page 7 of 11
M64893AGP
Electrical Characteristics
(Ta = -20C to 75Cunless otherwise noted)Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 s= 33 V
Parameters input terminals "H" input voltage "L" input voltage "H" input voltage "L" input current Lock output "H" output voltage "L" output voltage Band SW output voltage Leak current Tuning output output voltage "H" output voltage "L" Charge pump "H" output current "L" output current Leak current Supply current 1 Supply current 2 4circuits OFF 1 circuits ON, Output open Output current 40mA Supply current 3 Symbol Test pin Test conditions Limits Min VIH VIL IIH IIL VOH VOL VBS lOIK1 V to H V to L IOH IOL IcpLK ICC1 ICC2A ICC2B ICC2C ICC3C 13 to 15 13 to 15 13 to 15 13 to 15 12 12 5 to 8 5 to 8 10 10 9 9 9 3.0 -- -- -- 5.0 -- 11.6 -- 32.5 -- -- -- -- -- -- -- -- -- Typ -- -- -- -2 -- 0.3 11.8 -- -- 0.2 Max Vcc1+0.3 1.5 10 -10- -- 0.5 -- 1 -- 0.4 V V Unit
Vcc1 = 5.5 V, Vi = 4.0 V Vcc1 = 5.5 V, Vi = 0.4 V Vcc1 = 5.5 V Vcc1 = 5.5 V Vcc2 = 12 V lo = -40 mA Vcc2 = 12 V Band SW is OFF Vcc3 = 33 V Vcc3 = 33 V Vcc1 = 5.0 V Vo = 1 V Vcc1 = 5.0 V Vo = 1 V Vcc1 = 5.0 V Vo = 2.5 V Vcc1 = 5.5 V
A A
V V V
A
V V
250 50
-- 24 -- 5.0 45.0 3.6
470 130 50
31 0.5 6.0 46.0 4.5
A A
nA mA mA mA mA mA
4 4 4 11
Vcc2 = 12 V Vcc2 = 12 V Vcc2 = 12 V lo = -40 mA Vcc3 = 33 V Output ON
Note: The typical values are at Vcc1 = 5.0 V, Vcc2 = 12 V, Vcc3 = 33 V, Ta = 25C
Rev.1.00, Jul.25.2003, page 8 of 11
M64893AGP
Switching Characteristics
(Ta = -20C to 75C, Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameter Prescaler operating frequency Operating input voltage Symbol fopr Vin Test pin 1 1 13 Test conditions Vcc1 = 4.5 to 5.5 V Vin = Vinmin to Vinmax Vcc = 4.5 to 5.5 V 80 to 100 MHz 100 to 200 MHz 200 to 800 MHz 800 to 1000 MHz 1000 to 1300 MHz Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Limits Min 80 Min Max 1000 Unit used MHz dBm -24 -27 -30 -27 -24 1 2 1 3 3 1 -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4 4 4 4 -- -- -- -- -- -- 1 1 -- -- s s s s s s s s s s
Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time
t PWC t SU(D) t H(D) t SU(E) t H(E) t INT tr tf tbt tbcl
14 14 15 15 15,14 13,14,15 13,14,15 15 13.15
Rev.1.00, Jul.25.2003, page 9 of 11
M64893AGP
Application Example
BUILT-IN PLL TUNER
+5V
1000pF
+ 10 -
5 to 12 V
UHF VHF
3
M64893AGP
5
SW
18
Vcc2
+B
47k BS4 BS3 BS2 1 TEST M54938
fIN
4
BS4
11 12 13
47k 7 47k 47k 5
4-BAND T UNER
IF
BS3
6
BS2
IF
BS1
14
8 1000pF
BS1
MCU
14 2000pF 13 2000pF 2000pF 12 15
17 16 1000 pF 15 10
1500pF
Lo
3 4
DATA CLK EN LD
GND
AGC
AGC
2
20
51K
VT
/f 1/N X OUT
PD
15K
9 10
56K
56K 2200pF
AFT
9
XIN
*
100pF
GND
+5V 16
6
7
18pF 4MHz
8
11
Note) Filter constant is for reference. *Touch a capacitance because ilter circuit is instability.
+33V
BT
Unit Resisrance:
Rev.1.00, Jul.25.2003, page 10 of 11
M64893AGP
16P2Z-A
JEDEC Code - e b2 Weight(g) 0.08 Lead Material Cu Alloy
MMP
Plastic 16pin 225mil SSOP
Package Dimensions
EIAJ Package Code SSOP16-P-225-0.65
16
9
HE
E
L1
c z Z1 Detail G Detail F
L
Rev.1.00, Jul.25.2003, page 11 of 11
e1
Recommended Mount Pad F A
G
1
8
Symbol
D
b
x
M
e y x
A2
A1
A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2
Dimension in Millimeters Min Nom Max - - 1.9 0.05 - - - - 1.5 0.17 0.32 0.22 0.2 0.15 0.13 5.0 5.2 4.8 4.4 4.6 4.2 0.65 - - 6.2 6.5 5.9 0.4 0.6 0.2 0.9 - - - - 0.225 0.375 - - - 0.13 - 0.1 - - 0 - 10 - 0.35 - - 5.72 - - - 1.27
I2
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